Bachelor of Engineering Completion Certificate

 


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FM Synthesis using two Oscillators

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Abstract  Sounds that originate form nature have amplitudes of the frequency components that are ‘time variant’ or dynamic, partially due the uniqueness of the sound or in broader terms the randomness of the amplitude of each frequency in the particular sample. In an effort to convert digital sounds into a form that is ‘livelier’ an ADSR (Attack Delay Saturation and Release) envelopes were used. A sound envelop is a graph that dictates how a single note of sound would vary over time. This added a dynamic essence to the digital sounds. For example, with Attack envelope ‘bell’ like sounds with harsh overtones and prominent frequencies could be converted into an organ type sound by increasing the value of attack. However, for the longest time there lacked a process to synthesize organic/natural sounds. To put it simply, sounds that are random and that vary with time. In the September of 1973, John M Chowning submitted a paper for an algorithm for a process to produce complex natural s...
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GSM Based Remote Load Switching

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Abstract Today the energy meter is placed in the domestic or commercial sites and collects the data of the energy consumed and displays it on either a number dial or digital display. At the end of every billing cycle the person from the service provider has to visit the place where the meter is placed to get the reading and to note it down for further bill generation. The present system of energy charge is fallible and also long. So the purpose of this project is to develop an energy meter which is used to measure the consumer’s power consumption in kWh but also enable and support real consumption and, so meter reader does not need to visit each customer for the consumed data collection and to distributed the bill slip. The energy consumption is calculated using the measurement of voltage and current. It also continuously reads the energy meter readings and automatically sends some updates like low-balance alert, zero-balance alert, recharge alert when necessary, to the registered numb...
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RISC-V ALU: Design, Implementation, and Testing

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 Abstract This documentation presents the design and testing of an Arithmetic Logic Unit (ALU) model for a RISC-V architecture. The ALU is capable of performing various arithmetic and logical operations while also providing flags such as Carry, Overflow, Zero, and Negative. Introduction The ALU is a fundamental component of any processor, responsible for executing arithmetic and logical operations on data. In this documentation, we focus on an ALU designed for a RISC-V architecture, which is a popular instruction set architecture used in many modern processors. The ALU model presented here is implemented in Verilog and includes support for flags to provide information about the result of operations. ALU Model  Logic Diagram  Flags and Operations The ALU supports the following operations: Operation Description Addition Adds two numbers together. Subtraction Subtracts one number from another. Bitwise AND Performs a bitwise AND operation. Bitwise OR Performs a bitwise OR ope...
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