RISC-V ALU: Design, Implementation, and Testing

 Abstract

This documentation presents the design and testing of an Arithmetic Logic Unit (ALU) model for a RISC-V architecture. The ALU is capable of performing various arithmetic and logical operations while also providing flags such as Carry, Overflow, Zero, and Negative.

Introduction

The ALU is a fundamental component of any processor, responsible for executing arithmetic and logical operations on data. In this documentation, we focus on an ALU designed for a RISC-V architecture, which is a popular instruction set architecture used in many modern processors. The ALU model presented here is implemented in Verilog and includes support for flags to provide information about the result of operations.

ALU Model 

Logic Diagram 

Flags and Operations

The ALU supports the following operations:

Operation	Description
Addition	Adds two numbers together.
Subtraction	Subtracts one number from another.
Bitwise AND	Performs a bitwise AND operation.
Bitwise OR	Performs a bitwise OR operation.
Sign Extension	Extends the sign of a number.

The flags provided by the ALU are:

Flag	Description
Carry	Indicates if an arithmetic operation resulted in a carry out of the most significant bit.
Overflow	Indicates if an arithmetic operation resulted in an overflow condition.
Zero	Indicates if the result of an operation is zero.
Negative	Indicates if the result of an operation is negative.

Truth Table 

ALU Control	Operation	Input A	Input B	Result	Carry	Overflow	Zero	Negative
000	Addition	A	B	A + B	Carry	Overflow	Zero	Negative
001	Subtraction	A	B	A - B	Carry	Overflow	Zero	Negative
010	Bitwise AND	A	B	A & B	N/A	N/A	Zero	Negative
011	Bitwise OR	A	B	A | B	N/A	N/A	Zero	Negative
101	Sign Extension	A	N/A	Sign Ext	N/A	N/A	Zero

Test Cases

The provided test bench verifies the functionality of the ALU model with the following test cases:

Test Case	Operation	Inputs	Expected Result	Expected Flags
1	Addition	A = 5, B = 3	8	Carry = 0, Overflow = 0, Zero = 0, Negative = 0
2	Addition (Overflow)	A = 2147483647, B = 10	-2147483639	Carry = 1, Overflow = 1, Zero = 0, Negative = 1
3	Bitwise AND	A = 10, B = 4	0	Carry = 0, Overflow = 0, Zero = 1, Negative = 0
4	Sign Extension	A = 0xFFFFFFFF, B = 0x00000001	-1	Carry = 0, Overflow = 0, Zero = 0, Negative = 1
5	Subtraction (Negative)	A = 7, B = 10	-3	Carry = 0, Overflow = 0, Zero = 0, Negative = 1
6	Addition (Carry)	A = 0xFFFFFFFF, B = 1	0	Carry = 1, Overflow = 0, Zero = 1, Negative = 0
7	Addition	A = 5, B = 0	5	Carry = 0, Overflow = 0, Zero = 0, Negative = 0
8	Subtraction	A = 5, B = 5	0	Carry = 1, Overflow = 0, Zero = 1, Negative = 0

These test cases cover various scenarios including addition, subtraction, bitwise AND, and sign extension operations, along with different input values to verify the correctness of the ALU model. Test case practical results are provided below and are found to be in line with the expected results.

Waveform output

Scope

The ALU model presented here is designed to be used as a component within a larger RISC-V processor implementation. It provides the necessary arithmetic and logical functionality required for executing instructions in the processor.

Conclusion

In conclusion, the ALU model for a RISC-V architecture presented here demonstrates the essential arithmetic and logical operations required for processing instructions in a processor. By providing flags such as Carry, Overflow, Zero, and Negative, the ALU enhances the processor's capability to perform complex computations and handle different data types effectively. The comprehensive testing performed using the provided test bench validates the correctness and reliability of the ALU model, making it a valuable component in the development of RISC-V based processors.