End-to-End RTL to GDSII flow for digital clock circuit
Abstract: This project presents the design and implementation of a Digital Clock Circuit through a fully automated RTL-to-GDSII flow. The circuit performs precise timekeeping with features such as second, minute, and hour transitions. The project covers every stage of the VLSI design process, from initial preparation to layout verification, ensuring adherence to timing, power, and area constraints. Key steps include synthesis, placement, routing, static timing analysis (STA), and post-layout validation. The final output is a clean, manufacturable layout in GDSII format, ready for fabrication. Introduction: The Digital Clock Circuit is a vital module for accurate timekeeping in embedded systems and modern IC designs. This project demonstrates the end-to-end design flow for such a circuit, leveraging industry-standard tools and methodologies. By following a structured process, from Register Transfer Level (RTL) coding to final GDSII layout generation, this project ensures a robust a...