RISC-V ALU: Design, Implementation, and Testing
Abstract This documentation presents the design and testing of an Arithmetic Logic Unit (ALU) model for a RISC-V architecture. The ALU is capable of performing various arithmetic and logical operations while also providing flags such as Carry, Overflow, Zero, and Negative. Introduction The ALU is a fundamental component of any processor, responsible for executing arithmetic and logical operations on data. In this documentation, we focus on an ALU designed for a RISC-V architecture, which is a popular instruction set architecture used in many modern processors. The ALU model presented here is implemented in Verilog and includes support for flags to provide information about the result of operations. ALU Model Logic Diagram Flags and Operations The ALU supports the following operations: Operation Description Addition Adds two numbers together. Subtraction Subtracts one number from another. Bitwise AND Performs a bitwise AND operation. Bitwise OR Performs a bitwise OR ope...